SoC Verification Engineer - Design for Debug/Design For Test
Intel Corporation (company site, opens in a new tab)8+ yrsBengaluruOn-siteDirect career pageEst. 30–45 LPA
Posted 6h ago
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Job description
Structured overview of role & requirements
About This Role
- Own pre-silicon validation of SoC/IP Design-for-Debug features and DFT features such as TAP and scan using simulation, emulation and/or FPGA.
- Develop validation plans, Python emulation testcases and debug tools; investigate failures to root cause and improve debug flows across pre- and post-silicon teams.
- Support silicon debug and enabling, including collaboration with post-silicon validation software teams and development of tests to catch silicon failures in RTL models.
Minimum Requirements
- Work Experience Required: Minimum 8 years writing validation plans and software to implement them; minimum 4 years in DFD/DFT, programming/scripting with C, Python, Verilog and SystemVerilog, and computer architecture.
- Bachelor’s or master’s degree in Computer Science, Computer Engineering or Electrical Engineering.
- Demonstrated track record enabling and validating debug tools, resolving hardware/software debug issues to root cause, and working across validation, architecture, software, design and post-silicon teams.
Ideal Candidate Profile
- Has hands-on SoC or IP validation experience spanning pre-silicon debug and post-silicon support, with the ability to connect RTL behavior to silicon failures.
- Can turn written specifications and architecture into validation plans, tests and debug tooling, and drive adoption of useful tools and flows across teams.
- Candidates with experience in ATB, CoreSight, JTAG, emulation or Tessent align with preferred qualifications.