Director, SoC Design Verification and Virtual Platform Quality
Renesas Electronics Corporation (company site, opens in a new tab)15+ yrsHyderabadOn-siteDirect career pageEst. 40–65 LPA
Posted 6h ago
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Job description
Structured overview of role & requirements
About This Role
- Own verification strategy and sign-off across SystemC models, RTL, IP, subsystems, SoCs, and Virtual Platforms.
- Build reusable verification methods and automated regressions that carry test intent and quality evidence across modeling and implementation stages.
- Lead the global DV organization, including staffing, execution, risk management, partner engagement, and delivery reporting.
Minimum Requirements
- Work Experience Required: 15+ years in semiconductor IP, subsystem, or SoC Design Verification.
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Deep SystemVerilog and UVM expertise, including reusable environments, constrained-random testing, assertions, scoreboards, coverage, and closure; proven delivery of IP or SoC verification through sign-off.
- Experience leading geographically distributed verification teams and multiple concurrent programs; strong regression automation, metrics, and release-quality governance experience.
Ideal Candidate Profile
- Has verified SystemC/TLM models and can connect their verification to RTL through bridges, common tests, functional-equivalence checks, or timing correlation.
- Can establish risk-based, reusable verification across IP-to-platform integration while maintaining delivery schedules and evidence-based release gates.
- Has led complex debug and organizational execution across RTL, modeling, software, validation, and product teams.