Senior Formal Verification Engineer
Intel Corporation (company site, opens in a new tab)10+ yrsBengaluruOn-siteDirect career pageEst. 35–55 LPA
Posted 12h ago
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Job description
Structured overview of role & requirements
About This Role
- Own end-to-end formal verification of interconnect fabrics, protocol bridges, and link-layer logic across multiple protocol domains, from property specification through proof convergence.
- Define verification scope and plans, build abstraction models, generate and debug proofs, and improve formal infrastructure and methodologies.
- Track verification progress and drive technical reviews with architecture, RTL, physical design, and software teams to meet schedule and quality goals.
Minimum Requirements
- Work Experience Required: 10+ years of relevant formal verification experience.
- BTech/MTech in Electrical Engineering, Computer Science, or a related field.
- Proficiency in formal verification tools and methods, including model checking and equivalence checking; strong SystemVerilog, Verilog, logic, and microarchitecture fundamentals; experience with abstraction, simulation, and convergence strategies; familiarity with BDDs and DFGs.
- Role is based in Bangalore, India, and follows a hybrid work model.
Ideal Candidate Profile
- Has deep formal verification expertise and can independently carry proofs from specification through convergence across several protocol domains.
- Brings silicon interconnect, protocol, bridge, or link-layer verification experience and can model complex architectural and microarchitectural behavior.
- Works across architecture, design, and physical-design interfaces, improves verification tooling and methods, and can contribute to mentoring junior engineers.