Design Verification Architect
Candescent (company site, opens in a new tab)15+ yrsBengaluruOn-siteDirect career pageEst. 45–70 LPA
Posted 1d ago
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Job description
Structured overview of role & requirements
About This Role
- Own the formal verification architecture and strategy for PCIe and UALink controller IP, from block through end-to-end verification.
- Build reusable SVA, properties, checkers, and formal verification IP; drive proof convergence, coverage closure, and debug of complex RTL issues.
- Set formal coverage and proof-completeness measures, identify verification gaps, and guide the balance of formal, simulation, emulation, and system-level verification; mentor verification engineers.
Minimum Requirements
- Work Experience Required: Typically 15+ years of verification experience, including at least 5 years of hands-on formal verification.
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Deep expertise in property-based formal verification of complex RTL, including SystemVerilog/SVA, assumptions and constraints, abstraction/decomposition, proof closure, and counterexample debug; hands-on experience with Cadence Jasper or an equivalent formal platform.
- Deep PCIe knowledge and experience applying formal verification to high-speed interconnect or networking controller designs; experience with UALink, CXL, UCIe, Ethernet, or a comparable protocol is also specified.
Ideal Candidate Profile
- Has architected formal verification for complex, high-performance controller IP and can select high-value targets across protocol, flow-control, ordering, recovery, and resource-management logic.
- Can make difficult proofs tractable using compositional methods, abstraction, invariants, partitioning, and proof-debug techniques.
- Works closely with RTL architects and designers to resolve design ambiguities early, improve design-for-formal, and extend formal capability across a verification organization.