RTL Synthesis Methodology Principal/ Sr Staff Engineer
Qualcomm Incorporated (company site, opens in a new tab)15+ yrsBengaluruOn-siteDirect career pageEst. 50–90 LPA
Posted 19h ago
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Job description
Structured overview of role & requirements
About This Role
- Lead the definition, development, and global deployment of RTL Synthesis Reference Flows across advanced technology nodes (5nm, 3nm, 2nm+).
- Drive RTL-to-Gate co-optimization initiatives to enhance Power, Performance, Area (PPA), collaborating with RTL, Physical Design teams, and EDA vendors.
- Own Logic Equivalence Checking (LEC) and Static Timing Analysis (STA) signoff flows ensuring robust methodology and quality, while mentoring CAD engineers and managing vendor relationships.
Minimum Requirements
- 15+ years experience in ASIC CAD flow development, Physical Design, or Synthesis Methodology.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Expertise in Synopsys Fusion Compiler/Design Compiler and Cadence Genus synthesis tools.
- Proven hands-on experience with Logic Equivalence Checking tools (Cadence Conformal LEC, Synopsys Formality) and Static Timing Analysis (PrimeTime).
Ideal Candidate Profile
- Experienced leader able to influence and manage cross-site synthesis methodology and project stakeholders in a high-technology environment.
- Strong technical expertise integrating synthesis with low power methodologies (UPF/CPF), physical synthesis, and DFT flows.
- Skilled in flow automation scripting (Tcl, Python) and knowledgeable about AI/ML tools for CAD optimization is a strong plus.