Staff/ Sr Staff/Principal Engineer, STA
Renesas Electronics Corporation (company site, opens in a new tab)8–15 yrsBengaluruOn-siteDirect career pageEst. 30–55 LPA
Posted 2h ago
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Job description
Structured overview of role & requirements
About This Role
- Own the RTL-to-Gate conversion process including hierarchical and physical-aware synthesis to optimize performance, power, and area (PPA).
- Execute block-level and full-chip Static Timing Analysis (STA) across multi-mode, multi-corner scenarios and collaborate with PNR teams for timing closure.
- Architect and manage block-level and top-level constraints including UPF for multi-power domains and implement low-power architectures.
Minimum Requirements
- 8-15 years of experience in synthesis and STA closure on complex designs.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Proficiency with EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC.
- Strong scripting skills in Tcl, Python, or Perl for automation; experience with UPF and multi-voltage domain implementation.
Ideal Candidate Profile
- Experienced in managing STA closure on high frequency and complex designs with deep understanding of clock structures (functional and DFT).
- Skilled in physical-aware synthesis optimizing congestion, critical path restructuring, and datapath optimizations to meet PPA targets.
- Ability to architect constraint development and collaborate cross-functionally for timing closure and design convergence.