Senior Engineer Design Verification - Rx
Greenwave Systems (company site, opens in a new tab)5+ yrsBengaluruOn-siteDirect career pageEst. 14–26 LPA
Posted 2h ago
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Job description
Structured overview of role & requirements
About This Role
- Lead design verification of ORAN packet processing and high-speed SERDES interfaces using internal Python reference models and UVM testbenches.
- Develop and execute comprehensive verification plans, including SoC-level testbenches, HW/SW co-verification, and debug to achieve functional and code coverage goals.
- Support emulation, FPGA, automated verification flows, and collaborate with firmware teams to convert DV sequences to firmware drivers.
Minimum Requirements
- Bachelor's or Master's degree in Engineering (EC/EE/CS).
- 5+ years experience in ORAN protocol design verification using reference models.
- Proficient in SystemVerilog, Verilog, UVM, C, Python, Perl, Tcl/Shell scripting.
- Experience with Cadence vManager for DV metrics extraction and regression.
Ideal Candidate Profile
- Experienced in integrating Python/C++ models into UVM environment and developing Agents and Scoreboards for network functional blocks.
- Strong understanding and hands-on expertise in verification lifecycle, testbench development, and constrained random verification.
- Comfortable working with complex SoC-level verification and HW/SW co-verification environments in a fast-paced product launch setting.