Lead Engineer Design Verification
Greenwave Systems (company site, opens in a new tab)8+ yrsBengaluruOn-siteDirect career pageEst. 22–40 LPA
Posted 2h ago
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Job description
Structured overview of role & requirements
About This Role
- Lead verification efforts for ARM Cortex CPU subsystems and O-RAN Packet Processor blocks using SystemVerilog/UVM and Python/C++ reference models.
- Develop and execute comprehensive test plans and SoC-level verification environments, covering interfaces like PCIe, Ethernet, SerDes, and on-chip protocols (AMBA AXI/AHB).
- Collaborate with architects, RTL designers, firmware, and cross-functional teams to ensure verification coverage closure, support hardware emulation, FPGA prototyping, and automate verification flows.
Minimum Requirements
- 8+ years of experience in design verification with expertise in constrained-random verification, assertion-based verification, and reference-model verification.
- Bachelor's and/or Master's degree in Engineering (EC/EE/CS or equivalent).
- Proficiency in SystemVerilog, UVM, C/C++, and scripting languages like Python, Perl, Tcl, Shell.
- Experience verifying ARM Cortex-based CPU subsystems, O-RAN packet processing, and high-speed interfaces including PCIe, Ethernet, SerDes.
Ideal Candidate Profile
- Strong background in SoC-level design verification, especially with ARM CPU subsystems and O-RAN packet processing systems.
- Experienced in developing reusable verification components and integrating software-driven verification and hardware/software co-verification.
- Comfortable working in complex multi-disciplinary teams involving design, firmware, and system engineering with strong debugging and problem-solving skills.