Senior Staff Digital Methodology Engineer - Design for Testability (DFT)
Synopsys (company site, opens in a new tab)10+ yrsBengaluruOn-siteDirect career pageEst. 35–60 LPA
Posted 1d ago
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Job description
Structured overview of role & requirements
About This Role
- Define and drive advanced DFT methodologies for large-scale ASIC and SoC designs, including deployment of scan compression, hierarchical DFT, and IJTAG instrumentation.
- Lead technical strategy and implementation of test access architectures using multiple IEEE standards across multi-die and chiplet-based systems.
- Develop automation frameworks and reusable methodologies to improve engineering productivity and influence TestMAX product roadmap based on customer engagements.
Minimum Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 10+ years semiconductor or EDA industry experience; minimum 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies.
- Hands-on experience with Synopsys TestMAX DFT and ATPG tools in production and strong expertise in scan insertion, compression, hierarchical DFT, and coverage optimization.
- Proficiency in scripting languages (Tcl, Python, Perl) for automation; deep knowledge of IEEE 1149.1, 1149.6, 1687, and 1500 test standards.
Ideal Candidate Profile
- Senior-level engineer with demonstrated success architecting and deploying DFT solutions for multi-billion-gate ASICs and SoCs including successful tapeouts.
- Strategic thinker who can engage with both executive leadership and engineering teams to influence product roadmaps and resolve complex DFT challenges.
- Experienced in automation as a core deliverable and driving methodology adoption enterprise-wide, familiar with advanced node semiconductor processes and manufacturing realities.