Principal Digital Methodology Engineer - Design for Testability (DFT)
Synopsys (company site, opens in a new tab)15+ yrsBengaluruOn-siteDirect career pageEst. 45–85 LPA
Posted 1d ago
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Job description
Structured overview of role & requirements
About This Role
- Define and drive advanced DFT methodologies and best practices for multi-billion-gate ASIC and SoC designs, focusing on tapeout schedules and silicon success.
- Lead deployment and architect scalable test access infrastructures across multi-die and chiplet systems using major IEEE standards.
- Develop automation frameworks and reusable methodology packages to accelerate adoption across Synopsys business units and provide technical leadership in customer engagements and internal escalations.
Minimum Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 15+ years in semiconductor or EDA industry with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies.
- Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions in production design environments.
- Proficiency in Tcl, Python, Perl, or Shell scripting for methodology automation and deployment.
Ideal Candidate Profile
- Proven track record architecting and delivering DFT solutions for large-scale, complex ASICs and multi-billion-gate SoCs with successful tapeouts.
- Strategic thinker comfortable engaging with executive stakeholders and engineering teams to influence DFT architecture and product roadmaps.
- Experienced in deploying IEEE 1149.1, 1149.6, 1687, and 1500 standards in advanced node silicon test architectures and driving automation as a core scalable methodology component.