Senior Engineer Design Verification - Tx
Greenwave Systems (company site, opens in a new tab)5+ yrsBengaluruOn-siteDirect career pageEst. 15–28 LPA
Posted 4h ago
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Job description
Structured overview of role & requirements
About This Role
- Lead design verification for 5G wireless DSP blocks ensuring bit-true and cycle accurate RTL verification.
- Develop and maintain UVM testbench environments and verification plans collaborating with architects and designers.
- Implement HW/SW co-verification environments, execute and debug test cases, and drive verification coverage and metrics achievement.
Minimum Requirements
- Bachelor's or Master's degree in Engineering (EE/EC/CS) or equivalent.
- 5+ years experience in DSP block design verification using reference MATLAB/Python models.
- Proficiency in SystemVerilog, UVM, Verilog, C, and scripting languages (Python, Perl, Tcl/Shell).
- Experience with Cadence vManager, GIT, JIRA, and handling full verification lifecycle including test plan, testbench development, and coverage closure.
Ideal Candidate Profile
- Experienced in integrating MATLAB/Python DSP models into UVM environment creating verification components like agents and scoreboards.
- Strong knowledge of wireless communication theories including SNR, IQ constellations, FFT, OFDM, MIMO.
- Capable of independently developing complex IP/subsystem/chip-level verification environments and driving verification closure in a fast-paced product launch context.