Lead Engineer – CAD Digital Verification
Silicon Labs (company site, opens in a new tab)7+ yrsHyderabadOn-siteDirect career pageEst. 22–38 LPA
Posted 9h ago
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Job description
Structured overview of role & requirements
About This Role
- Develop and maintain CAD tools and EDA simulation flows for Design Verification, Formal Verification, Low Power, Functional Safety, and Coverage Analysis of ASIC/SoC products.
- Create and optimize automation scripts (Python, Perl, Tcl, Bash) to streamline digital simulation, testbench generation, and verification workflows improving engineering productivity and design quality.
- Collaborate with RTL designers, verification teams, and EDA vendors (Cadence, Synopsys, Siemens EDA) to integrate new capabilities, resolve simulation bottlenecks, and support debugging of complex simulation failures.
Minimum Requirements
- Bachelor’s degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
- Minimum 7+ years industry experience with a Bachelor’s degree, or 5+ years with a Master’s degree, in Design Verification, CAD/EDA tool development, or ASIC/SoC verification flow support.
- Hands-on programming experience in Python, Perl, Tcl, C/C++, shell scripting and familiarity with RTL, Verilog/SystemVerilog, and UVM verification environments.
- Experience with Linux/UNIX environments and use of EDA simulation tools for digital verification workflows.
Ideal Candidate Profile
- Experienced in developing scalable verification automation frameworks and improving simulation performance across multiple engineering teams.
- Demonstrated capability to debug complex EDA tool issues and collaborate directly with EDA vendors to resolve technical challenges.
- Strong understanding and practical experience with ASIC/SoC verification methodologies, including formal verification, low power verification, and functional safety contexts.