Senior Staff - Design Verification Engineer
Tylsemi12–16 yrsBengaluruOn-siteDirect career pageEst. 35–65 LPA
Posted 1d ago
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Job description
Structured overview of role & requirements
About This Role
- Lead the definition and execution of scalable and reusable verification architectures for complex, large SoCs targeting AI, HPC, and Networking applications.
- Architect and develop modular verification platforms with high coverage-driven testbenches using industry-standard methodologies like UVM and Portable Stimulus (PSS).
- Drive multi-level verification strategies from block to full-chip level, incorporating AI/ML techniques to automate testbench generation, improve regression efficiency, and ensure first-pass silicon success.
Minimum Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 12 to 16 years of experience in Design Verification with significant exposure to large SoC verification.
- Proven experience in defining and deploying verification architectures for complex chips with expertise in SystemVerilog, UVM, coverage-driven and assertion-based verification, and Portable Stimulus.
- Strong understanding of SoC architectures in AI, HPC, or Networking domains and experience with protocols like PCIe, Ethernet, CXL, UCIe.
Ideal Candidate Profile
- Strong architectural thinker with a systems-level mindset and experience handling multi-IP integration and complex system-level debugging.
- High ownership and quality-first approach with a bias for automation, reuse, scalability, and adoption of AI-driven verification technologies.
- Ability to work effectively in a fast-paced environment driving fail-fast methodologies and collaborating closely with cross-functional teams.