Lead Engineer - CAD Physical Verification
Silicon Labs (company site, opens in a new tab)5+ yrsHyderabadOn-siteDirect career pageEst. 18–30 LPA
Posted 8h ago
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Job description
Structured overview of role & requirements
About This Role
- Own development and support of physical verification (PV) rule decks such as DRC, Antenna, Dummy fill, and custom decks during chip design cycles.
- Lead impact analysis meetings, collaborate with CAD, ESD, Design, Layout, Packaging, and foundry teams to gather requirements and ensure deck quality.
- Develop, maintain, and automate PV flows and methodologies to optimize verification quality and performance; evaluate new tools and work with vendors to address software bugs.
Minimum Requirements
- 5+ years of professional experience in physical verification or related field.
- Bachelor’s or Master’s degree in electrical engineering.
- Proficiency in developing DRC decks using Calibre SVRF or similar languages; experience with LVS, extraction, and PERC decks is a plus.
- Experience with physical verification tools like PVS, Pegasus, Calibre RVE, Calibre DRV, and scripting languages PERL/Python/Shell.
Ideal Candidate Profile
- Experienced in cross-functional collaboration with design, layout, packaging, and foundry teams to translate specs into PV rule decks and lead decision-making.
- Skilled in debugging PV issues in chip design and driving impact analysis with stakeholders.
- Comfortable working independently with strong documentation and communication skills to manage technical discussions and code reviews.