Physical Design Automation Engineer
Intel Corporation (company site, opens in a new tab)BengaluruOn-siteDirect career pageEst. 35–70 LPA
Posted 8h ago
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Job description
Structured overview of role & requirements
About This Role
- Lead development and continuous improvement of RTL-to-GDS flows using Cadence Innovus for end-to-end physical design automation.
- Define and drive physical design tools, flows, and methodologies including floorplanning, placement, CTS, routing, and timing closure on advanced process nodes.
- Enable and support Innovus-based APR flows for internal and external design customers, collaborating with CAD teams and EDA vendors to ensure scalable, production-ready solutions.
Minimum Requirements
- Master's degree (M.Tech or MS) in Microelectronics, Electronics Engineering, or equivalent from a reputed institute.
- Proven hands-on experience with Cadence Innovus Implementation System for block-level RTL-to-GDS physical design flow development and closure.
- Strong understanding of digital timing concepts and experience with industry-standard STA tools such as Cadence Tempus.
- Work Model: On-site presence required at Bangalore, India. Work Experience Required: Not explicitly mentioned in the JD.
Ideal Candidate Profile
- Experienced technical lead in physical design automation with demonstrated leadership in block-level closure and tape-out sign-off.
- Deep expertise in Cadence Innovus-based PnR and strong knowledge of all key physical design stages and optimizations for advanced nodes.
- Proven collaborator working across internal design, CAD, and EDA vendor teams, able to deliver robust, scalable APR automation in a complex product and foundry environment.