Staff/Senior Staff Physical Verification CAD engineer
Marvell Technology, Inc. (company site, opens in a new tab)5–12 yrsBengaluruOn-siteDirect career pageEst. 30–50 LPA
Posted 7h ago
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Job description
Structured overview of role & requirements
About This Role
- Develop and automate physical verification CAD tools and flows for semiconductor design, including support for DRC and LVS debugging using Calibre and Synopsys ICV.
- Lead and support tape-out and design-related foundry interface activities, SOC integration CAD flows, and validation of physical verification procedures.
- Collaborate cross-functionally to maintain and optimize CAD/EDA tools performance, create documentation, and deliver training to ensure design productivity and quality.
Minimum Requirements
- Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.
- 5 to 12 years total professional experience, with at least 5 years in CAD and EDA tool development and support in the semiconductor industry.
- Proficiency with EDA tools and methodologies, including Cadence, Synopsys (ICV required), Mentor Graphics (Calibre preferred), and scripting languages such as Tcl, Perl, Python.
- Eligibility to access export-controlled technology as per U.S. export control laws (EAR) is required.
Ideal Candidate Profile
- Experienced in full IC design flow with strong expertise in both digital and analog IC physical verification and design automation.
- Demonstrated leadership in driving CAD/EDA projects, providing technical guidance, and mentoring junior engineers in a semiconductor environment.
- Strong capability in tool integration, methodology development, and collaboration with foundry, design, and software teams to optimize semiconductor design productivity.