Senior Lead Engineer - Verification
L&T Technology Services Limited (company site, opens in a new tab)12–17 yrsBengaluruOn-siteDirect career pageEst. 35–50 LPA
Posted 21h ago
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Job description
Structured overview of role & requirements
About This Role
- Lead verification strategy and architecture across IP, Subsystem, and SoC levels for next-generation semiconductor products.
- Define and develop reusable SystemVerilog/UVM verification environments, plans, and methodologies ensuring first-silicon success.
- Provide technical leadership and mentoring to verification teams, driving functional coverage closure and quality standards.
Minimum Requirements
- 12 to 17 years of relevant work experience.
- Bachelor of Technology (BTech) degree.
- Proficiency in SystemVerilog and UVM methodologies.
- Experience with scripting languages such as Python, Perl, Shell, or Tcl for automation.
Ideal Candidate Profile
- Experienced technical leader comfortable driving verification strategy from architecture through signoff for complex SoCs and IPs.
- Strong system-level mindset with ability to collaborate across cross-functional teams including RTL, analog/mixed-signal, firmware, and post-silicon validation.
- Proven track record in mentoring engineers, developing reusable verification IPs, and improving verification productivity and methodologies.