PDK Deck Developer
NXP Semiconductors (company site, opens in a new tab)15+ yrsNoidaOn-siteDirect career pageEst. 35–60 LPA
Posted 10h ago
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Job description
Structured overview of role & requirements
About This Role
- Lead and manage the Process Design Kit (PDK) Physical Verification (PV) team responsible for development, testing, and customer support of PDK PV rule decks and related tools.
- Drive continuous quality improvement, productivity enhancements, and efficiency alignment across technologies using AI tools and advanced methodologies.
- Coordinate cross-geographic teams for PDK PV release planning, method refinement, and system integration to ensure robust PDK infrastructure and customer satisfaction.
Minimum Requirements
- 15+ years of experience in PDK Physical Verification rule deck development/support or related physical verification methodologies (DRC, LVS, ERC, PERC, fill, parasitic, EMIR).
- Mandatory experience with Calibre SVRF/TVF rule deck coding OR Cadence PVS/Assura rule deck coding.
- Proficiency with tools such as Calibre, CalibreXRC, Assura, Cadence PVS, Synopsys ICV, Virtuoso, Cadence QRC, StarRCXT, Voltus, Redhawk.
- Bachelor's or Master's degree in Electrical or Electronics Engineering or a related discipline.
Ideal Candidate Profile
- Deep expertise in foundry-based and EDA tool based process variation formats and EMIR challenges, reflecting strategic technical leadership.
- Proven track record in managing and enhancing PDK PV teams and processes leveraging AI and automation to drive innovation and efficiency.
- Experience working in cross-geographic teams with strong ownership of PDK PV planning, release, and quality assurance methodologies.