Sr Engineer CAD Pre-Silicon Front End - Bangalore
Velaura8+ yrsBengaluruOn-siteDirect career pageEst. 30–55 LPA
Posted 1d ago
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Job description
Structured overview of role & requirements
About This Role
- Own end-to-end front end automation flows from RTL entry to handoff into DFT and physical implementation, including build, lint, CDC, formal checks, register generation, and interface flows.
- Manage design verification flows: testbench development, regression execution, coverage, emulation and FPGA prototyping build and bring up.
- Develop, deploy, and maintain AI-assisted tools across design and verification workflows, ensuring flow availability and productivity improvements through the entire design cycle.
Minimum Requirements
- Minimum 8 years experience in design verification, design, or CAD engineering with ownership of a flow area.
- Strong expertise in SystemVerilog and RTL design/debugging; Solid Python programming skills for tool development and maintenance.
- Experience with simulation and regression flows, front end EDA tools (Synopsys, Cadence, Siemens EDA), Linux system administration, distributed computing (LSF, Slurm), and large-scale storage solutions.
- Work Experience Required: Minimum 8 years in relevant engineering roles.
Ideal Candidate Profile
- Experienced in managing live front end engineering flows with fast issue resolution and collaboration with design and verification teams.
- Skilled at building sustainable tools used by engineers, with a focus on improving productivity and operational stability.
- Familiarity with advanced verification environments (UVM, cocotb), emulation and FPGA prototyping platforms, and applying AI/LLMs to engineering workflows preferred.