SoC Verification Senior Lead Engineer
NXP Semiconductors (company site, opens in a new tab)12–15 yrsBengaluruOn-siteDirect career pageEst. 28–45 LPA
Posted 0m ago
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Job description
Structured overview of role & requirements
About This Role
- Own development and execution of SoC-level and IP-level verification suites for complex ARM-based microcontrollers with defined coverage goals.
- Develop, debug, and run UVM-based verification environments and test cases across RTL, power-aware RTL, gate-level, FPGA, and emulation platforms.
- Drive design verification closure for diverse IPs and subsystems ensuring maximum coverage and quality; mentor junior engineers and collaborate with design teams for issue resolution and sign-off.
Minimum Requirements
- 12-15 years of experience in SoC/IP verification with proven participation in successful SoC tape-outs.
- Strong expertise in ARM-based microcontrollers, SoC-level verification, and C-based DV methodologies.
- Proficiency in Verilog, SystemVerilog, UVM, constrained-random verification, and familiarity with Synopsys VCS and Cadence Xcelium EDA tools.
- Mandatory experience in low-power verification (UPF), gate-level simulations, and power-aware simulations; Bachelors or Masters in Microelectronics, Electronics, or Electrical Engineering.
Ideal Candidate Profile
- Experienced in formal verification techniques and capable of operating both SoC-level and IP-level verification environments.
- Skilled in verification of multiple interfaces (SPI, I²C, UART, CAN, eSPI) and knowledgeable about Flash memory and security IPs (nice to have).
- Operates well in fast-paced environments, demonstrates strong collaboration skills, and actively mentors junior team members.