Staff Verification Design Engineer
Semtech Corporation (company site, opens in a new tab)3+ yrsHyderabadOn-siteDirect career pageEst. 12–22 LPA
Posted 1d ago
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Job description
Structured overview of role & requirements
About This Role
- Lead block and chip-level verification across RTL, gate-level, and analog/mixed-signal domains including simulation and formal verification.
- Develop and execute verification strategies and detailed plans in collaboration with design teams to ensure tape-out quality.
- Support post-silicon bring-up, debug, and enhance verification environments and automation for scalability and portability across projects.
Minimum Requirements
- 3+ years experience in semiconductor industry.
- M.S. degree in Electrical Engineering, Computer Science, or Computer Engineering or higher.
- Hands-on expertise with System Verilog and UVM verification methodology, plus debugging digital simulations at module and system level.
- Scripting skills in Python or Perl; clear understanding of ASIC design flow; location requirement: Onsite.
Ideal Candidate Profile
- Experienced in establishing UVM verification environments from scratch and automating verification processes in real-world projects.
- Skilled in both digital verification and analog behavioral modeling or verification.
- Capable of independent ownership in verification with strong analytical skills and able to coordinate verification perspectives in design/project reviews.