Design Verification Engineer- AI Accelerator - Bangalore
Velaura8+ yrsBengaluruOn-siteDirect career pageEst. 30–55 LPA
Posted 1d ago
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Job description
Structured overview of role & requirements
About This Role
- Own verification of custom AI acceleration units including matrix and vector compute engines in a Physical AI SoC.
- Develop detailed test and coverage plans from microarchitectural intent, verifying numerical correctness, performance, and energy efficiency.
- Build and maintain verification environments using SystemVerilog, UVM, C/C++, perform regressions, debug complex failures, and support emulation and pre-silicon bring-up.
Minimum Requirements
- 8+ years experience verifying high performance compute or complex digital designs.
- Proficient in SystemVerilog, UVM, C/C++, assertions, and coverage-driven verification methodologies.
- Bachelor's or higher degree in Computer Engineering, Electrical Engineering, or Computer Science.
- High level understanding of LLMs including transformer structure and inference data flow, plus knowledge of GEMM/GEMV operations mapped to hardware.
Ideal Candidate Profile
- Experienced in independently owning full verification lifecycle of compute hardware blocks, including test planning and coverage closure.
- Strong background in numerical formats (FP16, BF16, FP8, INT8) and verification of precision, rounding and quantization behavior against architecture specs.
- Familiarity with accelerator data flow for AI workloads, including throughput, latency, and performance per watt targets under LLM and vision workloads.