Lead Software Engineer
Cadence Design Systems, Inc. (company site, opens in a new tab)5+ yrsNoidaOn-siteDirect career pageEst. 18–35 LPA
Posted 7h ago
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Job description
Structured overview of role & requirements
About This Role
- Own the end-to-end design, development, validation, and delivery of Formal Verification IPs including Verilog models and SystemVerilog Assertions for industry-standard protocols.
- Develop and maintain Assertion-Based Verification IPs with responsibility for architecture, implementation, validation, regression, release readiness, and documentation.
- Lead debugging of complex design and verification failures, automate flows using Python/Tcl, and mentor junior engineers while collaborating with global teams.
Minimum Requirements
- Bachelor's or Master's degree in Electrical/Electronics Engineering (BE/BTech/ME/MS/MTech).
- 5+ years experience in RTL design/verification if BE/BTech; 3+ years if Master's.
- Proficiency in Verilog/SystemVerilog RTL design or verification, verification planning, and coverage.
- Experience with at least one protocol such as AXI, CHI, PCIe, or CXL; Python and Tcl scripting skills.
Ideal Candidate Profile
- Experienced in formal verification methodologies and tools, preferably with knowledge of AI/ML concepts applied in verification or debugging.
- Capable of independently managing complex verification projects from planning through delivery with strong ownership and technical judgment.
- Effective communicator able to engage with customers and cross-functional global teams, and able to lead technical reviews and mentor others.