Staff Digital Verification Engineer
Renesas Electronics Corporation (company site, opens in a new tab)7+ yrsBengaluruOn-siteDirect career pageEst. 20–40 LPA
Posted 2h ago
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Job description
Structured overview of role & requirements
About This Role
- Own end-to-end verification of complex digital blocks or major SoC features, from requirements analysis through coverage closure.
- Develop and extend reusable SystemVerilog/UVM verification environments, including tests, assertions, checkers, and coverage models.
- Debug RTL, testbench, and integration failures; collaborate across architecture, design, firmware, analog, validation, and systems teams to isolate issues and verify fixes.
Minimum Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 7+ years of relevant digital design verification experience or equivalent directly applicable experience.
- Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions.
- Proficiency in Linux and at least one scripting language such as Python, Bash, Perl, or Tcl.
Ideal Candidate Profile
- Experienced in verification ownership of complex blocks or major SoC features, demonstrating disciplined verification completeness and risk management.
- Skilled in translating specifications into test plans and reusable verification IP in SystemVerilog/UVM with strong RTL and testbench debug capabilities.
- Collaborative working style with ability to communicate technical status and risks clearly across multidisciplinary teams, and interest in improving verification methodology and productivity.