Principal Engineer-Verification
Microchip Technology Inc. (company site, opens in a new tab)8+ yrsBengaluruOn-siteDirect career pageEst. 30–50 LPA
Posted 21h ago
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Job description
Structured overview of role & requirements
About This Role
- Own the verification of complex digital integrated circuits at block, subsystem, or device level using UVM methodology and SystemVerilog.
- Collaborate with chip architects, subsystem leads, Software and Validation teams to deliver verified, compliant, and error-free designs.
- Lead verification planning, testbench development, test execution, and contribute to enhancing verification technologies and methodologies.
Minimum Requirements
- Bachelor's or Master's Degree in Electrical Engineering or Computer Engineering.
- 8+ years of related work experience in digital IC verification or a related field.
- Proficient in SystemVerilog, UVM, and verification methodologies including formal verification and constrained-random verification.
- Strong coding skills in SystemVerilog/Verilog/VHDL and scripting languages such as Tcl/Perl/Python; excellent English communication skills.
Ideal Candidate Profile
- Experienced in designing and verifying digital integrated circuits with ownership of verification at various levels (block, subsystem, or device).
- Operates effectively in cross-functional teams involving design, software, and validation, indicating a collaborative and technical leadership style.
- Demonstrates adaptability to new verification methodologies and technologies with strong debugging and analytical skills.