Staff Design Verification Infrastructure Engineer - VIPs and Testbench
SiFive (company site, opens in a new tab)BengaluruOn-siteDirect career pageEst. 35–60 LPA
Posted 10h ago
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Job description
Structured overview of role & requirements
About This Role
- Develop and maintain SiFive's Verification Platform including VIPs, AIPs, and testbench components to support scalable Design Verification efforts.
- Architect and enhance verification libraries and components in Scala (with Chisel), System Verilog, and UVM to express verification intent and build test harnesses, stimulus, and scoreboards.
- Create and execute test plans/testbenches to ensure high-quality releases of verification infrastructure and educate verification teams on best practices.
Minimum Requirements
- Experience in Design Verification using System Verilog and UVM with demonstrated work on VIPs, AIPs, and testbench components.
- Strong understanding of software engineering practices relevant to verification infrastructure development.
- Right to work in India is mandatory; subject to background and reference checks plus export control authorization.
- Work Experience Required: Not explicitly mentioned in the JD.
Ideal Candidate Profile
- Experienced Design Verification engineer with a solid foundation in software engineering practices, comfortable with both hardware verification and software-driven infrastructure development.
- Familiarity with Scala and Chisel environments for testbench library development is a strong advantage, indicating ability to work with SiFive’s custom verification platform.
- Ability to collaborate across teams by educating others and contributing to scalable verification solutions for a growing chip design organization.