Senior CAD Engineer – Physical Design Signoff
Intel Corporation (company site, opens in a new tab)8+ yrsBengaluruOn-siteDirect career pageEst. 30–55 LPA
Posted 8h ago
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Job description
Structured overview of role & requirements
About This Role
- Develop and enhance automation solutions for Physical Design signoff flows including RC Extraction, Static Timing Analysis, Electrical Rule Checking, and Power Integrity.
- Analyze and resolve signoff issues, improve signoff quality, convergence, and turnaround time by driving methodology improvements.
- Collaborate with design and CAD teams, EDA vendors to deploy new signoff capabilities, and build dashboards for monitoring signoff health and project readiness.
Minimum Requirements
- M.Tech/M.S. in Electrical Engineering, VLSI, Computer Engineering, or related field.
- 8+ years of industry experience in Physical Design, Signoff, CAD, or Design Automation.
- Strong proficiency in Python, Tcl, and Shell scripting.
- Work Location: India, Bangalore; Work model: Hybrid.
Ideal Candidate Profile
- Deep expertise in Parasitic Extraction, Static Timing Analysis, Electrical Rule Checking, and Power Integrity signoff.
- Experience with advanced process technologies (3nm, 2nm, Intel 18A/14A) and variation-aware timing methodologies.
- Familiarity with power delivery networks, EM analysis, reliability signoff, and large-scale signoff infrastructure.