Senior CAD Engineer - Floor Plan
Intel Corporation (company site, opens in a new tab)4+ yrsBengaluruOn-siteDirect career pageEst. 20–40 LPA
Posted 8h ago
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Job description
Structured overview of role & requirements
About This Role
- Own and maintain Design Planning and RTL to Floorplan methodologies for CPU IP programs, ensuring efficient deployment across multiple projects.
- Develop and enhance automation frameworks and analytics infrastructure to improve physical design flow quality, productivity, and scalability.
- Provide technical support to physical design teams by debugging flow, tool, and methodology issues; and drive continuous methodology improvements and adoption of new EDA capabilities.
Minimum Requirements
- M.Tech/MS in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or related field.
- Minimum 4 years of industry experience in CAD Engineering, Design Automation, Physical Design Methodology, EDA Tool Development, or Physical Design Infrastructure.
- Strong knowledge of Physical Design flows, RTL-to-Floorplan methodologies, design planning concepts, and PPA analysis.
- Proficient in software development and scripting languages including Python, Tcl, and Shell scripting.
Ideal Candidate Profile
- Experienced in supporting CPU Core, Cache, Fabric, or other high-performance IP design teams with physical implementation methodologies.
- Demonstrated expertise in building and maintaining production-quality CAD automation frameworks and deploying physical-aware RTL design planning flows.
- Familiar with advanced technology nodes (e.g., Intel 18A/14A, TSMC N3/N2), distributed compute/cloud infrastructures, and the application of ML/AI techniques to EDA tool and methodology improvement.