DSP / NPU Design Verification Sr Staff Engineer
Qualcomm Incorporated (company site, opens in a new tab)12+ yrsBengaluruOn-siteDirect career pageEst. 45–80 LPA
Posted 20h ago
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Job description
Structured overview of role & requirements
About This Role
- Lead design verification for complex DSP/NPU IP cores critical to Qualcomm’s SoC roadmap across mobile, AI, and automotive domains.
- Develop, implement, and improve System Verilog/UVM testbench architectures and verification methodologies to meet coverage and quality targets.
- Drive debugging and verification activities from IP to subsystem and SoC levels using simulation, formal verification, power-aware verification, and automation tools.
Minimum Requirements
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years; Master's with 5+ years; or PhD with 4+ years in Hardware Engineering or related experience.
- Minimum 12+ years experience in processor/ASIC design verification specifically in DSP/NPU IP or similar complex IP verification.
- Proficiency in System Verilog/UVM, digital design concepts, power aware verification, assertion-based verification, and gate-level simulation with relevant tool suites (Synopsys/Mentor/Cadence).
- Experience with scripting languages (Perl, Python, Shell) for automation and strong debugging skills required.
Ideal Candidate Profile
- Senior-level engineer with over a decade of hands-on expertise in processor or ASIC design verification, particularly in DSP or NPU architectures.
- Experienced in driving cross-functional verification efforts involving architecture, implementation, power, and post-silicon teams across globally distributed teams.
- Well-versed in advanced verification techniques including formal verification, power aware verification, and hardware/software co-verification, with a focus on delivering high quality, commercially successful silicon products.