Staff/ Sr Staff/Principal Engineer, STA
Renesas Electronics Corporation (company site, opens in a new tab)8–13 yrsBengaluruOn-siteDirect career pageEst. 30–55 LPA
Posted 14h ago
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Job description
Structured overview of role & requirements
About This Role
- Own RTL-to-Gate conversion including hierarchical and physical-aware synthesis to optimize performance, power, and area (PPA) targets.
- Perform block-level and full-chip static timing analysis (STA) for multi-mode multi-corner scenarios and provide signoff closure in collaboration with PNR team.
- Develop and manage constraint files (SDC/UPF), implement low-power architectures, and automate workflows using scripting (Tcl, Python, Perl).
Minimum Requirements
- 8-13 years of experience in synthesis and STA closure on complex ASIC designs.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Strong experience with physical-aware synthesis, STA signoff, and low-power implementation using UPF and multi-voltage domains.
- Proficient with EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC and scripting for flow automation.
Ideal Candidate Profile
- Experienced in handling high-frequency designs with deep knowledge of clock structures from functional and DFT perspectives to achieve timing closure.
- Capable of independently optimizing PPA through hierarchical synthesis and floorplan-driven techniques.
- Able to collaborate effectively with cross-functional teams including PNR and mentor junior engineers.