Engineer, Design Verification
Renesas Electronics Corporation (company site, opens in a new tab)1–2 yrsBengaluruOn-siteDirect career pageEst. 6–12 LPA
Posted 14h ago
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Job description
Structured overview of role & requirements
About This Role
- Own end-to-end verification execution for complex digital IPs and subsystems from specification through sign-off.
- Define and lead IP-level verification strategies including test plans, coverage models, and achieving closure criteria using metric-driven approaches.
- Develop scalable UVM-based verification environments and apply AI/ML-assisted techniques to accelerate coverage and optimize regression efficiency.
Minimum Requirements
- Bachelor’s or master’s degree in Electronics Engineering.
- 1-2 years of experience in SoC Verification with knowledge of EDA toolkits.
- Strong expertise in UVM-based testbench architecture, SystemVerilog, UVM, and verification methodologies including assertions (SVA) and coverage closure.
- Proficiency in directed and constrained-random verification methodologies and debugging across simulation, emulation, and post-silicon domains.
Ideal Candidate Profile
- Experienced in metric-driven verification focusing on thorough functional, code, assertion, and cross-coverage closure with demonstrable sign-off quality.
- Skilled in developing automated and reusable verification environments using UVM and scripting languages for analytics and automation.
- Familiar with advanced verification tools including AI/ML-assisted verification techniques and comfortable collaborating with cross-functional teams for IP integration and tool evaluation.