Staff Digital Verification Engineer
onsemi (company site, opens in a new tab)6–10 yrsBengaluruOn-siteDirect career pageEst. 18–35 LPA
Posted 1d ago
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Job description
Structured overview of role & requirements
About This Role
- Lead and own digital verification efforts across IP, subsystem, and SoC projects independently.
- Architect and develop reusable System Verilog and UVM verification environments, including constrained-random, directed, and scenario-based tests.
- Analyze and debug RTL and gate-level simulation failures; execute fault injection simulations to validate functional safety and fault handling.
Minimum Requirements
- 6-10 years of hands-on experience in Digital/ASIC/SoC Verification.
- Mandatory expertise in System Verilog and Universal Verification Methodology (UVM).
- Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
- Experience with Gate-Level Simulation and familiarity with simulators like Xcelium and Questa.
Ideal Candidate Profile
- Proven ability to independently lead verification projects from IP to SoC-level.
- Strong skills in coverage-driven verification and debugging complex RTL and gate-level issues.
- Experience integrating verification with multi-disciplinary teams (design, DFT, physical design, architecture) and working with AI-assisted engineering tools.