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Job Description
Structured overview of role & requirementsAbout This Role
Own ASIC verification of IP/Cluster for complex RTL designs including Graphics Processors and Tegra SOCs.
Plan and implement functional verification, develop regression plans, and ensure functional and code coverage closure.
Collaborate with HW architects, performance verification, FPGA, and software teams; support pre-silicon and post-silicon validation and debug activities.
Minimum Requirements
BS/MS degree or equivalent experience.
Minimum 1+ years of ASIC design experience with verification of complex design units on at least one or two projects.
Experience with ASIC verification tools such as VCS and debug tools like Debussy or GDB.
Familiarity with SystemVerilog and UVM-based ASIC verification methodology highly desired.
Ideal Candidate Profile
Experience with verification of Memory controllers or IP/clusters involving memory access is advantageous.
Strong debugging and problem-solving skills complemented by scripting knowledge (Python/Perl/shell).
Ability to work collaboratively across hardware, FPGA, and software teams supporting both pre- and post-silicon activities.