NPU Design Verification Sr Lead Engineer

Lead design verification of complex DSP/NPU IP by collaborating with global DSP design teams across architecture, implementation, power, and post silicon.

Develop, implement, and improve System Verilog/UVM testbench architecture and verification methodologies to meet coverage and quality goals.

Own verification activities including simulations, debugging at IP, subsystem, and SoC levels, gate level simulations with timing and power awareness, and usage of advanced verification tools such as assertions and formal verification.

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of hardware engineering or related work experience; OR Master's degree with 2+ years; OR PhD with 1+ year.

5+ years of experience specifically in design verification of complex DSP/NPU IP is required.

Proficiency in System Verilog/UVM testbench architecture and implementation, and experience with simulators such as Synopsys, Mentor, or Cadence.

Experience with gate level simulation, power aware verification, and scripting in Perl, Python, Shell, or Makefile.

Experienced in processor/ASIC design verification with a solid understanding of digital design and processor architecture including power aware verification.

Skilled at debugging complex failures across IP, subsystem, and SoC levels using advanced verification methods and tools.

Comfortable working in a multi-disciplinary global team environment driving high-quality semiconductor IP delivery for mobile, AI, and automotive markets.