NPU Staff Design Verification Engineer
Qualcomm IncorporatedMatch Score
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Job Description
Structured overview of role & requirementsAbout This Role
Lead design verification efforts for complex Qualcomm proprietary DSP/NPU IP involving architecture, implementation, and integration teams.
Develop, implement, and improve SystemVerilog/UVM testbench architectures and verification methodologies to meet coverage and quality goals.
Perform hands-on simulations and debug IP, subsystem, and SoC level bugs including gate-level and power-aware simulations.
Minimum Requirements
12+ years of experience in processor/ASIC design verification.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years experience; OR Master's degree with 5+ years; OR PhD with 4+ years experience in Hardware Engineering or related work.
Strong expertise in SystemVerilog/UVM Testbench architecture and implementation.
Experience with digital design, processor architecture verification, power aware verification, and verification tools (Synopsys/Mentor/Cadence simulators).
Ideal Candidate Profile
Experienced senior-level design verification engineer with deep knowledge of DSP processor architectures and subsystem verification.
Strong competency in advanced verification methodologies including formal verification, assertions, and power-aware verification.
Demonstrates ability to develop and automate comprehensive test plans and verification environments Collaborating effectively with global cross-functional hardware teams.