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Job Description
Structured overview of role & requirementsAbout This Role
Plan, develop, and execute emulation test content in system stress, cache coherency, and concurrency domains to verify next-gen microprocessor cores.
Collaborate with design and architecture teams to root-cause failures using advanced debugging techniques on hardware emulation platforms.
Create emulation models from RTL and develop/integrate high-performance transactors and test benches using SystemVerilog, SystemC/C++, and Python.
Minimum Requirements
M.Tech or B.Tech in Electronics Engineering or Computer Engineering.
2+ years semiconductor experience.
Strong software skills in compiled (C/C++) and interpreted (Python, Tcl) languages, and knowledge of SystemVerilog for design and verification.
Experience or knowledge in Cache coherency models, memory consistency (AArch64 and/or x86), and coherent interconnect protocols like AMBA CHI, AXI4, ACE.
Ideal Candidate Profile
Experience with emulation platforms such as Zebu, Palladium, Mentor Veloce, or FPGA prototyping preferred.
Proven skills in hardware/software co-debugging and bare-metal content development using C/C++ and ARM assembly.
Track record of independently driving verification innovations and working closely with cross-functional teams in a semiconductor design environment.