SoC Design Verification Engineer

Design and maintain UVM-based test benches and verification plans for SoC blocks, subsystems, and full chips to ensure functional correctness and high-quality performance.

Execute verification cycles including emulation and system simulations to detect and debug issues in presilicon environments, driving corrective actions.

Collaborate with architects, RTL developers, postsilicon validation teams, and physical design to improve verification coverage and methodology, incorporating feedback from postsilicon validation.

Bachelor's degree (Electrical Engg, Computer Engg, Computer Science) with 7+ years experience OR Master's degree with 6+ years in SoC design verification.

Proven expertise in OVM/UVM methodologies, test planning, and debugging for SoC verification.

Hands-on experience with AMBA protocols (CHI, AXI, AHB, APB) and associated industry-standard VIP from EDA vendors.

Location requirement: Bangalore, India with eligibility for hybrid work model.

Experienced in both pre-silicon functional verification and integrating postsilicon validation feedback to enhance verification strategies.

Comfortable working in cross-functional teams including architectural, RTL, and physical design groups in a large-scale semiconductor environment.

Strong technical capability in scalable verification plan development and debugging complex SoC designs emphasizing reuse and automation.