DV Power Vectors & Window Extraction Engineer (Staff/Sr Staff)

Develop and execute design verification (DV) power vectors for key workloads, power states, transitions, boot flows, retention, reset, and stress scenarios across simulation, emulation, and silicon-validation.

Analyze waveforms, activity dumps, and power reports to identify and document windows important for peak power, average power, dynamic voltage drop, thermal analysis, and pre/post-silicon correlation.

Maintain and debug power-aware verification environments including simulation and emulation; collaborate closely with multiple engineering teams to ensure vector collateral traceability and power-state correctness.

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or related field.

7-15 years of experience in design verification, power-aware verification, vector development, or power analysis.

Strong understanding of RTL simulation, waveform analysis, SystemVerilog/UVM or equivalent, low-power design concepts, and power estimation techniques.

Proficiency in scripting languages such as Python, Perl, Shell, or Tcl; experience using waveform debug and power-analysis tools.

Expertise in power-vector development with strong debugging skills and ability to identify representative corner-case power windows.

Experienced in cross-functional collaboration in complex engineering environments involving DV, design, power, physical design, emulation, and post-silicon teams.

Familiarity with low-power design principles, power-aware verification flows, and correlation of pre-silicon simulations with post-silicon measurements.