Staff Engineer IP Verification - Digital Design Verification

Own and lead verification efforts for complex block-level custom designs with advanced low power and power management technologies across DRAM generations including DDR5, LPDDR5, DDR6, LPDDR6 operating up to 11,4000MT/s.

Define verification scope, strategy, plans and develop SV-UVM based testbenches, execute directed and constrained-random tests with coverage closure towards tapeout readiness.

Provide technical leadership, mentor junior engineers, influence verification methodology, and coordinate verification efforts across geographically distributed teams, including adopting AI tools for verification workflow enhancement.

Bachelor’s degree with 7-9 years experience or Post Graduate degree with 6-8 years experience in Electronics Engineering or related field.

Hands-on experience with digital simulation tools and methodologies including SystemVerilog and UVM for block-level RTL verification.

Previous work experience in DRAM memory related fields and proficiency with tools such as Virtuoso, Xcellium, Simvision, Verdi/Verisium.

Good scripting skills in Perl and Python; proactive adoption and responsible use of AI tools in verification workflows.

Experienced in leading end-to-end verification for complex, high-speed memory IP blocks, particularly in DRAM architectures and features.

Able to provide technical leadership and mentorship in a multi-location, collaborative environment with strong communication and debugging skills.

Skilled in integrating verification methodologies and new verification flows, including the application of AI tools to improve productivity and verification quality.