NOC Emulation Staff Engineer

Develop and optimize emulation-based pre-silicon verification environments for complex SoCs using hardware-assisted verification platforms like Cadence Palladium, Synopsys ZeBu, and Siemens Veloce.

Analyze and debug emulation failures by root-causing RTL, testbench, or software issues; collaborate with design teams to resolve bugs and improve verification quality.

Automate regression executions and improve emulation infrastructure efficiency, including mentoring junior engineers and participating in cross-functional verification planning.

Bachelor's or Master's degree in Electronics, Electrical, Computer Engineering, or related field.

4+ years (Bachelor) or 3+ years (Master's) of experience in Design Verification and/or Emulation.

Strong proficiency in SystemVerilog and UVM with experience in hardware-assisted verification platforms (Cadence Palladium, Synopsys ZeBu, Siemens Veloce).

Expertise in synthesizable testbench development, transaction-based acceleration, debugging tools (Verdi, DVE, SimVision), and scripting languages (Python, Perl, Shell).

Experienced in SoC-level verification, including software-driven and long-running workloads, with a focus on reducing verification turnaround time and improving bug discovery.

Skilled in cross-functional collaboration with RTL, DV, Architecture, Firmware, and Post-Silicon teams, and contributing to reusable, scalable emulation infrastructure.

Capable of improving and driving continuous enhancements in emulation methodologies and mentoring junior engineers to uphold best practices.