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Job Description
Structured overview of role & requirementsAbout This Role
Develop and execute verification test benches, including drivers, monitors, and response checkers using UVM and system Verilog.
Translate requirements into traceable verification plans and create simulation cases covering various scenarios with constrained-random stimulus.
Perform RTL code analysis, debug functional failures, assertion coverage, and root cause analysis to ensure correctness of SoC/subsystem designs.
Minimum Requirements
5-10 years of experience in SoC/Subsystem verification involving complex multi-million gate designs.
Strong hands-on expertise in C and UVM/SV test environments, Verilog or VHDL, and simulators like Synopsys, Cadence, or Mentor.
Bachelor's or Master's degree in Technology (BTech/MTech).
Experience with microcontroller architectures, ARM cores, interconnects (NIC, FlexNoC), cache coherency, and bus protocols (AHB, AXI, ACE).
Ideal Candidate Profile
Experienced in coverage-driven verification and regression management for complex SoC projects.
Skilled at debugging RTL/Gate netlists and interpreting functional and assertion coverage for large multi-clock/power domain designs.
Familiar with advanced verification methodologies like formal verification, low power verification (CPF, UPF), and VIPs related to memory controllers and common protocols (PCIe, MIPI, GPU, Ethernet, USB).