Staff Engineer Verification -IP Digital Functional Verification
Infineon Technologies AGMatch Score
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Job Description
Structured overview of role & requirementsAbout This Role
Lead verification subtasks for complex IP/SoC designs, ensuring thorough functional verification coverage.
Develop and maintain IP/SoC level verification requirements, UVM testbenches, and formal verification environments.
Support development of verification infrastructure including RTL simulation, power-aware verification, and gate-level simulation as required.
Minimum Requirements
Bachelor's degree in Electrical/Electronics Engineering or Master's in VLSI Design or related field.
Minimum 5+ years of relevant ASIC verification experience.
Strong proficiency in Verilog, SystemVerilog, UVM and hands-on experience with verification environment development.
Knowledge of power-aware verification, gate-level verification and exposure to formal verification techniques is highly desirable.
Ideal Candidate Profile
Experienced in IP/SoC verification across diverse applications and design domains with proven ability to develop complex testbenches.
Comfortable leading verification efforts in a technically complex environment involving RTL simulation, formal, power-aware, and gate-level verification.
Has strong analytical and debugging skills with effective communication and stakeholder collaboration capabilities.