Staff Engineer- AMS Verification

Develop and implement advanced SystemVerilog real-number modeling methodologies for analog/mixed-signal (AMS) verification to optimize pre-silicon validation speed and accuracy.

Collaborate with design and verification teams to define functional verification plans ensuring proper AMS block integration in complex SoC architectures.

Create and maintain custom verification frameworks and behavioral models (VerilogAMS, SystemVerilog) compatible with digital simulation environments; identify and resolve AMS verification flow bottlenecks.

Proven experience in AMS verification for complex SoCs and subsystem-level designs.

Strong proficiency with mixed-signal simulation tools such as Cadence Xcelium + Spectre, Synopsys XA-VCS, or Mentor Eldo ADMS.

Hands-on experience with behavioral modeling including Verilog-D, Verilog-A, and Verilog-AMS.

Work Experience Required: Not explicitly mentioned in the JD.

Experienced in leading technical AMS verification projects within multi-site, global teams.

Strong functional knowledge of analog and mixed-signal components such as comparators, op-amps, ADCs/DACs, and power management architectures.

Skilled in scripting/automation using Python, Perl, Tcl, SKILL or equivalent, and familiar with SystemVerilog and UVM testbench development from a mixed-signal perspective.