DFX Verification Engineer

Lead design verification for Design for Debug (DfX) architectures including test case and testbench creation using UVM methodology.

Define and implement verification strategies, methodologies, and test plans for full chip and system level functional verification covering SoC, FPGA, and full chip designs.

Coordinate cross-functional efforts among Design, Software, and Architecture teams to achieve comprehensive verification coverage and use system-level applications to verify performance and identify issues.

5+ years of experience with complex ASIC design and/or verification.

Proficiency in System Verilog and UVM verification methodology; formal verification knowledge required.

Experience in Design for Debug architectures (e.g. JTAG, High speed USB, PCIe debug) and their design verification.

Location requirement: Bengaluru, Karnataka, India; Flexible to work Shift 1 (India) timings.

Experienced in pre-silicon system verification with strong understanding of SoC, FPGA, and full chip design verification environments.

Skilled at cross-functional coordination with design, software, and architecture teams for verification planning and execution.

Familiarity with ARM and RISC debug architectures and scripting skills in Linux/Unix environments (Perl/Python) to enhance verification processes.