Senior Staff Design Verification Engineer SOC
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Job Description
Structured overview of role & requirementsAbout This Role
Develop and debug testbenches, testcases, and checkers to validate SoC design behavior against specifications.
Manage verification tasks independently and contribute to enhancing design verification (DV) flows and methodologies.
Collaborate with cross-functional teams to identify and resolve design bugs and discrepancies.
Minimum Requirements
Bachelor’s degree in Electrical/Computer Engineering, Computer Science, or related field.
8-10 years of experience in SoC verification.
Proficient in SystemVerilog, UVM, C, and scripting languages such as Python, Tcl/Tk, and Perl.
Understanding of SoC interconnects and bus standards (AXI, AHB, APB).
Ideal Candidate Profile
Experienced in hands-on SoC design verification with strong debugging and testbench development skills.
Able to independently manage verification projects and mentor junior engineers.
Collaborative approach working with cross-functional teams to ensure design quality and verification completeness.