Senior SOC Verification Engineer - Networking
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Job Description
Structured overview of role & requirementsAbout This Role
Lead integration and verification for SOC-level projects including cluster, sub-system and full chip verification.
Develop verification infrastructure and automated flows using advanced methodologies such as e-specman, SV-UVM.
Collaborate with architects, designers and QA teams to ensure high test coverage and hardware quality across pre-silicon, emulation and post-silicon phases.
Minimum Requirements
Bachelor’s or Master’s degree in Electrical and Electronics Engineering (EEE) or Electronics and Communication Engineering (ECE).
At least 4 years of experience in design verification.
Strong coding skills in SystemVerilog, scripting languages (Python, Perl), and C++.
Experience with logic design, verification tools (Verilog/SV, Cadence or equivalent), and familiarity with debug tools such as Indago and GDB.
Ideal Candidate Profile
Experience in verification of SmartNICs or Data Processing Units (DPUs) and/or high-speed interconnects.
Proven ability to debug, solve problems and analyze complex hardware verification issues.
Exposure to multi-team coordination across time zones and experience with cluster/sub-system/SoC level environments.