Technical Staff Engineer-Verification

Own verification strategy, architecture, and technical leadership for communication semiconductor devices and subsystems.

Lead verification efforts including planning, testbench architecture, coverage closure, and sign-off readiness at block and top device levels.

Mentor a small team of Verification Engineers and collaborate cross-functionally to deliver production-quality devices with comprehensive verification evidence.

Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering required.

12+ years of related experience in digital integrated circuit verification.

Proficiency in SystemVerilog, UVM, assertions, constrained-random testing, and coverage-driven verification methodologies.

Strong coding skills with experience in SystemVerilog/Verilog/VHDL, Tcl/Perl/Python, C/C++ and familiarity with Synopsys, Cadence, or similar verification tool flows.

Experienced in verification of complex digital integrated circuits with leadership in verification strategy and architecture.

Deep knowledge of communication protocols such as Ethernet and verification methodologies relevant to networking semiconductors.

Ability to integrate verification strategy with product requirements and cross-functional teams, driving closure and quality for advanced semiconductor devices.