Principal ASIC Digital Design Engineer (Verification)
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Job Description
Structured overview of role & requirementsAbout This Role
Architect and implement unified verification flows and scalable verification infrastructure for Synopsys digital IP and SoC projects using Synopsys tools (VCS, Verdi, VMS Execution Manager, Verdi Planner, VIP).
Define, document, and propagate verification methodologies and best practices as standards across Synopsys digital IP projects.
Lead and mentor verification engineers and independently manage technical initiatives from concept to deployment, collaborating with global teams and EDA tool developers.
Minimum Requirements
10+ years of hands-on experience in IP or SoC verification with technical leadership in complex verification environments.
Expertise in Synopsys verification tools: VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IP (VIP).
Proficient in SystemVerilog, UVM, Tcl, and Python programming and scripting for automation and flow development.
Bachelor's degree in Electronics, Electrical, or Computer Engineering; advanced degrees are a plus.
Ideal Candidate Profile
Experienced in architecting verification flows for complex digital designs with a systems-level approach rather than scripting only.
Skilled at balancing and managing multiple high-impact verification projects independently across global teams and time zones.
A strategic thinker able to communicate complex technical tradeoffs clearly and mentor engineers, driving adoption and continuous learning within verification teams.