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Job Description
Structured overview of role & requirementsAbout This Role
Build and implement unified verification flows for Synopsys digital IP products using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
Lead and mentor verification engineers, providing technical guidance and managing high-impact technical projects independently from concept to deployment.
Collaborate with global teams and EDA tool development groups to standardize verification methodologies, optimize workflows, and influence product roadmaps.
Minimum Requirements
4+ years of hands-on experience in IP or SoC verification with leadership in technical initiatives and complex verification environments.
Deep expertise in Synopsys verification tools: VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IP (VIP).
Proficient programming/scripting skills in SystemVerilog, UVM, Tcl, and Python for automation and flow development.
Bachelor's degree in Electronics, Electrical, or Computer Engineering; advanced degrees are a plus.
Ideal Candidate Profile
Experienced in architecting scalable verification infrastructures for complex digital designs supporting global teams.
Capable of managing multiple verification projects simultaneously with strategic prioritization and clear technical communication across cross-functional teams.
Demonstrates hands-on technical leadership in UVM/SystemVerilog testbench debugging and applying data-driven improvements to methodologies and workflows.