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Job Description
Structured overview of role & requirementsAbout This Role
Own and architect end-to-end silicon signoff CAD flow strategy including parasitic extraction, static timing analysis, power integrity, and physical verification for advanced-node silicon programs.
Drive quality improvements through industry practices, quality metrics, and validation frameworks to prevent silicon escapes and reduce re-spins.
Lead engagement with EDA vendors, collaborate with design teams for signoff convergence, and establish technical standards for signoff engineering team growth.
Minimum Requirements
Bachelor's in Electrical, Computer Engineering or related field with 8+ years technical engineering experience OR Master's with 6+ years OR Doctorate with 3+ years OR equivalent experience.
Experience working with advanced-node (5nm or below) silicon signoff CAD tools including StarRC/Pegasus, PrimeTime/Tempus, Redhawk-SC/Voltus, Fusion Compiler/Innovus.
Ability to pass Microsoft Cloud Background Check and meet export control legal requirements involving citizenship or residency verification.
Not explicitly mentioned in the JD: Notice period requirements or specific location constraints.
Ideal Candidate Profile
10+ years hands-on silicon signoff CAD engineering experience with demonstrated zero-escape silicon quality on multiple concurrent tapeouts at 5nm or below.
Strong expertise across both Synopsys and Cadence tool ecosystems for parasitic extraction, timing, power, and physical design implementation with scripting and automation skills in TCL/Python.
Experience leading technical growth, establishing scalable reusable flow architectures, and working effectively with geographically distributed teams in cloud-based EDA compute environments.